This relates generally to integrated circuit packages, and more particularly, to integrated circuit packages with decoupling capacitor circuitry.
An integrated circuit package typically includes an integrated circuit die and a substrate on which the die is mounted. The die is often coupled to the substrate through bonding wires or solder bumps. Signals from the integrated circuit die may then travel through the bonding wires or solder bumps to the substrate.
As integrated circuit technology scales towards smaller device dimensions, device performance continues to improve at the expense of increased power consumption. In an effort to reduce power consumption, more than one die may be placed within a single integrated circuit package (i.e., a multi-chip package). As different types of devices cater to different types of applications, more dies may be required in some systems to meet the requirements of high performance applications. Accordingly, to obtain better performance and higher density, an integrated circuit package may include multiple dies arranged laterally along the same plane or may include multiple dies stacked on top of one another.
A multi-chip package can include multiple dies mounted on an interposer. Each of the multiple dies may include decoupling capacitors. Decoupling capacitors are used to help provide more stable power supply voltages by shunting high frequency noise on direct current (DC) power supply lines to ground, thereby preventing the noise from reaching powered circuit components. In a scenario in which a power supply is required to switch between various modes of operation, an adequate decoupling capacitance can act as an energy reserve that lessens the magnitude of undesired dips in power supply voltage during mode switching events.
Vias are typically formed in the interposer and can serve as routing paths through which power supply signals are conveyed to each of the multiple dies in the multi-chip package. Parasitic capacitance, inductance, and resistance associated with the vias in the interposer may contribute to elevated levels of power distribution network (PDN) resonance noise. This may require increasing the amount of decoupling capacitance that are formed on the multiple dies within the multi-chip package to help compensate for this elevated noise. The need for additional decoupling capacitor circuitry could occupy a disproportionate amount of valuable die area.